SK Hynix Tall 16-High HBM3E 48GB (Sample/Production)

The SK Hynix 16-High HBM3E 48 GB represents a landmark achievement in high-bandwidth memory engineering, extending the HBM3E die stack from the previous 12-high configuration to a full 16-layer arrangement. By adding four additional DRAM dies to each stack, SK Hynix increases per-package capacity from 36 GB to 48 GB while preserving the 1024-bit wide interface that defines the HBM architecture. The stack is fabricated using SK Hynix's advanced process node and employs Through-Silicon Via (TSV) interconnects throughout all 16 dies, enabling signal integrity and thermal management at densities previously unachievable in production-grade HBM. This 48 GB capacity per package allows GPU and AI accelerator designers to equip a single accelerator card with up to 288 GB or more of HBM3E when using six stacks, dramatically raising the memory ceiling for large-model inference and training without increasing the physical footprint of the memory subsystem.

Operating at a nominal 9.6 Gbps per pin, each 16-high HBM3E stack sustains up to 1.2 TB/s of aggregate bandwidth, matching or exceeding the per-stack bandwidth of its 12-high predecessor while doubling usable capacity per stack. This bandwidth-to-capacity ratio is critical for transformer-based large language models, diffusion models, and scientific simulation workloads where the working dataset must reside entirely in on-package memory to avoid costly off-chip data movement. The memory array is organized across 16 independent DRAM dies, each connected via the base logic die that manages refresh, error correction, and the physical interface to the host accelerator through a standardized HBM PHY. On-die ECC is implemented per die, and the base logic die aggregates advanced system-level ECC, providing robust data integrity assurance required for continuous, multi-day AI training runs.

The 16-High HBM3E 48 GB is designed specifically for integration into next-generation AI training accelerators, high-performance computing GPUs, and custom ASIC-based AI chips manufactured on advanced interposer or 2.5D packaging platforms. Its introduction in 2025-Q4 positions it as the highest-capacity single HBM stack commercially available, enabling accelerator vendors to architect systems targeting 100-billion-parameter and trillion-parameter model training without sharding memory across nodes. The sample and production availability schedule allows accelerator and system integrators to begin validation cycles alongside accelerator silicon tape-outs, ensuring co-optimization of the memory subsystem with next-generation AI compute dies.

Ideal for

• Large Language Model (LLM) pre-training on 100B+ parameter transformer architectures where the full model and optimizer states must reside in on-package memory to maximize GPU utilization
• Generative AI inference serving for multimodal foundation models requiring extremely low first-token latency, achieved by keeping all KV-cache and weight tensors in high-bandwidth on-chip memory
• High-Performance Computing (HPC) simulations including molecular dynamics, climate modeling, and computational fluid dynamics that demand both high memory capacity and sustained memory bandwidth above 1 TB/s per accelerator
• Recommendation system training using embedding tables exceeding 30 GB per accelerator, where 48 GB per stack eliminates the need for embedding table partitioning across multiple devices
• AI accelerator ASIC development and bring-up, where the 48 GB 16-high stack serves as the memory subsystem in prototype and production silicon designed on advanced 2.5D CoWoS or similar interposer platforms
• Graph neural network (GNN) training on trillion-edge graphs requiring large working-set memory capacity co-located with compute to avoid PCIe or NVLink bandwidth bottlenecks

Technical specifications

Available from Omnixon Global. Submit an RFQ and our team will confirm configuration and availability for your order.