Micron HBM3E 36GB 12-High

The Micron HBM3E 36GB 12-High is a cutting-edge High Bandwidth Memory solution built on the HBM3E specification, stacking 12 DRAM dies to achieve an unprecedented 36GB capacity per stack. Fabricated using Micron's advanced 1-beta DRAM process node, each stack integrates thousands of through-silicon vias (TSVs) connecting the dies vertically, enabling a 1024-bit wide memory interface that operates at data rates exceeding 9.2 Gbps per pin. This architecture delivers an aggregate bandwidth of 1.2 TB/s per stack — a critical enabler for next-generation AI accelerators, training clusters, and scientific computing platforms that require both massive memory capacity and extreme data throughput in a thermally and spatially constrained package.

Designed for integration into advanced packaging substrates such as silicon interposers and fan-out wafer-level packages, the HBM3E 36GB 12-High is purpose-built for pairing with high-end AI training GPUs, inference accelerators, and HPC ASICs. The 12-high stacking approach — one base logic die plus 12 DRAM core dies — pushes the density boundary of HBM technology while maintaining tight power efficiency metrics. With an operating voltage of approximately 1.1V and a thermal design envelope optimized for liquid- or advanced air-cooled server environments, the module achieves best-in-class GB/W efficiency ratios essential for hyperscale data center deployments running continuous, sustained AI workloads.

Launched in Q2 2025, the Micron HBM3E 36GB 12-High represents a significant leap over the preceding HBM3 generation, offering higher per-stack capacity, greater bandwidth, and improved signal integrity at scale. Its adoption is targeted at systems training large language models (LLMs), diffusion-based generative AI models, and graph neural networks where memory-bound operations dominate execution time. The device fully conforms to JEDEC HBM3E standards, ensuring interoperability with compliant accelerator SoCs from leading silicon vendors and providing enterprise customers with a clear, standards-backed roadmap for multi-generational AI infrastructure investments.

Ideal for

• Large language model (LLM) training across thousands of GPU nodes where memory bandwidth saturation directly limits transformer layer throughput
• Generative AI inference serving for diffusion models and multimodal architectures requiring fast KV-cache access and low-latency tensor operations
• High-performance computing workloads such as molecular dynamics, climate simulation, and computational fluid dynamics that are strongly memory-bandwidth bound
• Graph analytics and graph neural network training on trillion-edge datasets requiring high-capacity, high-throughput memory to hold adjacency structures
• Financial risk modeling and Monte Carlo simulations running on GPU-accelerated servers where rapid random-access memory throughput reduces time-to-result
• AI supercomputer node design where system architects integrate multiple HBM3E stacks per accelerator die to maximize aggregate system memory bandwidth beyond 10 TB/s per node

Technical specifications

Available from Omnixon Global. Submit an RFQ and our team will confirm configuration and availability for your order.