SK Hynix HBM3E 36GB 8-Hi Stack (Palloc)

The SK Hynix HBM3E 36GB 8-Hi Stack, codenamed Palloc, represents the leading edge of high-bandwidth memory technology, engineered specifically for the demands of large-scale AI training, inference, and HPC acceleration platforms. Built on SK Hynix's advanced HBM3E process node, this 8-Hi stacked configuration integrates nine DRAM dies—one base logic die plus eight core dies—connected through thousands of through-silicon vias (TSVs) and micro-bumps, achieving a 36GB per-stack capacity that enables significantly larger AI model parameters and activation tensors to reside directly on-package memory rather than requiring costly off-chip transfers.

Operating at a per-stack bandwidth exceeding 1.2 TB/s, the Palloc stack leverages a 1024-bit wide interface running at data rates consistent with the HBM3E specification, delivering roughly 40% greater bandwidth compared to its HBM3 predecessors. The architecture employs advanced ECC schemes, pseudo-channel mode for improved access granularity, and on-die thermal sensors to support the rigorous reliability and manageability requirements of datacenter-class AI accelerators and GPU clusters. The stack is designed to interface directly with GPU and AI ASIC packages via 2.5D silicon interposer or CoWoS-style packaging, enabling extremely low latency and energy-efficient memory access.

Launched in Q2 2025, the Palloc positions itself as a critical enabler for the next generation of AI accelerators from major silicon vendors, supporting workloads such as large language model (LLM) training at scale, diffusion model inference, scientific simulation, and seismic processing. Its increased per-stack density means fewer stacks may be required to meet memory capacity targets, improving system-level power efficiency and board-space utilization while simultaneously raising the ceiling for model complexity and batch throughput.

Ideal for

• Large language model (LLM) training on multi-GPU clusters where on-package memory bandwidth is the primary throughput bottleneck
• High-throughput LLM and multimodal inference serving requiring low-latency access to billions of model parameters simultaneously
• Scientific HPC workloads including molecular dynamics, climate modeling, and computational fluid dynamics that demand sustained memory bandwidth
• AI accelerator SoC design and validation where HBM3E stacks are integrated via CoWoS or silicon interposer into next-generation AI ASICs
• Diffusion model and generative AI image/video synthesis requiring rapid traversal of large activation maps stored in on-package memory
• Seismic imaging and geophysical processing pipelines that move petabyte-scale datasets through GPU memory at maximum sustainable bandwidth

Technical specifications

Available from Omnixon Global. Submit an RFQ and our team will confirm configuration and availability for your order.