Samsung HBM3E 36GB Cube

The Samsung HBM3E 36GB Cube represents the fourth generation of Samsung's High Bandwidth Memory architecture, built on 12-layer stacked DRAM dies connected through thousands of through-silicon vias (TSVs). Manufactured on Samsung's advanced 1c-nm DRAM process node, each cube integrates 36 gigabytes of capacity with a 1,024-bit wide interface per stack, enabling aggregate bandwidth exceeding 1.2 terabytes per second per package. This dramatic leap in bandwidth density is achieved through refined micro-bump interconnect pitch, improved ECC architecture, and a refined power delivery network that reduces operating voltage while sustaining higher data rates at HBM3E-class speeds up to 9.8 Gbps per pin.

Designed explicitly for integration alongside flagship AI training and inference GPUs, the HBM3E 36GB Cube targets accelerator designers building hardware for large language model (LLM) training, scientific simulation, and high-performance computing workloads. The expanded 36GB per-stack capacity — a 50% increase over previous-generation 24GB HBM3 stacks — allows GPU die complexes to maintain larger working datasets in-package, significantly reducing PCIe or NVLink traffic to external DRAM or storage tiers. The cube ships with full AiM (Aquabolt-in-Memory) readiness at the architecture level, supporting potential near-memory compute extensions in forthcoming accelerator generations.

Launched in Q1 2025, the Samsung HBM3E 36GB Cube advances thermal management through a redesigned top-die heat spreader interface and tighter package coplanarity tolerances, facilitating reliable direct liquid cooling integration in high-density server trays. Samsung's in-package ECC covers both the DRAM arrays and the TSV interconnect fabric, delivering robust data integrity at the extreme throughput rates demanded by petaflop-class AI clusters. The device complies with JEDEC HBM3E standards, ensuring interoperability with silicon interposers and advanced packaging substrates from leading logic foundries.

Ideal for

• Large language model pre-training on multi-GPU nodes where per-accelerator memory capacity and bandwidth directly constrain achievable batch sizes and model parallelism efficiency
• High-performance inference serving for billion-parameter transformer models requiring sub-millisecond token generation latency with full model weights resident in on-package memory
• Computational fluid dynamics and finite-element analysis workloads on GPU clusters that require streaming terabytes of mesh data per second through the memory subsystem
• Genomics and molecular dynamics simulations that exploit massive bandwidth to sustain high FLOP utilization on memory-bound algorithms across distributed accelerator arrays
• Graph neural network training over billion-node graphs where irregular memory access patterns benefit from the low-latency, high-bandwidth characteristics of stacked HBM3E
• Custom ASIC and FPGA-based AI accelerator products where hardware designers integrate HBM3E cubes via silicon interposer to achieve competitive memory subsystem performance

Technical specifications

Available from Omnixon Global. Submit an RFQ and our team will confirm configuration and availability for your order.