AMD EPYC 9555 (Turin, 64-core Zen 5)

The AMD EPYC 9555 is a 4th-generation EPYC processor (codenamed Turin) built on the Zen 5 microarchitecture, manufactured on TSMC's advanced 4nm process node. Featuring 64 cores and 128 threads within a 360W TDP envelope, the 9555 targets the high-volume enterprise server segment where organizations must balance raw compute performance against software licensing models that charge per core. The Zen 5 architecture introduces a redesigned front-end with wider decode, improved branch prediction, and a larger floating-point execution unit that delivers approximately 17% higher instructions-per-clock compared to Zen 4, making every core meaningfully more productive across both integer and floating-point workloads.

The EPYC 9555 integrates 256MB of AMD 3D V-Cache is absent on this SKU, keeping latency characteristics ideal for throughput-oriented and bandwidth-sensitive workloads rather than cache-bound applications. It supports up to 6TB of DDR5 memory across 12 channels at speeds up to DDR5-6400, and provides 128 PCIe 5.0 lanes per socket for connecting high-speed NVMe storage, 400GbE network adapters, and GPU accelerators without bandwidth bottlenecks. The SP5 socket ensures platform continuity with existing EPYC 9004-series infrastructure investments.

As AMD's flagship mid-tier Turin SKU, the EPYC 9555 is particularly compelling for two-socket server deployments where aggregate core count, memory capacity, and I/O density matter as much as single-thread frequency. Its 3.2 GHz base clock and 4.0 GHz boost frequency, combined with Zen 5's architectural improvements, provide a substantial generational uplift in enterprise database, virtualization, and cloud-native workloads. The processor is fully supported under AMD EPYC's enterprise ecosystem including NUMA-aware operating systems, VMware vSphere, Red Hat OpenShift, and leading HPC schedulers.

Ideal for

• Large-scale enterprise virtualization with VMware vSphere or KVM, where 64 cores per socket maximize VM density while keeping per-core licensing overhead manageable across two-socket deployments
• In-memory relational and analytical databases such as Oracle, SAP HANA, and Microsoft SQL Server, leveraging 12-channel DDR5 for sustained high memory bandwidth and low-latency access to large working sets
• Cloud-native Kubernetes and OpenShift platforms hosting high-density microservices workloads where per-core CPU threading directly maps to container scheduling efficiency
• High-performance computing (HPC) simulation and scientific modeling workloads in energy, life sciences, and financial risk analytics, benefiting from Zen 5's enlarged floating-point pipelines and 128 PCIe 5.0 lanes for GPU co-processor connectivity
• Enterprise-scale AI inference serving using GPU accelerators connected via PCIe 5.0, where the CPU handles pre- and post-processing while feeding low-latency data to discrete inference engines
• Software-defined storage controller nodes running Ceph or similar distributed storage platforms, exploiting high core counts for parallel I/O handling, erasure coding, and data integrity operations

Technical specifications

Available from Omnixon Global. Submit an RFQ and our team will confirm configuration and availability for your order.