Samsung HBM3E 12-High 36GB DRAM Stack

The Samsung HBM3E 12-High 36GB DRAM Stack represents the pinnacle of High Bandwidth Memory technology, extending the HBM3E generation to a 12-die vertical stack configuration that yields 36 gigabytes of capacity per package. Built on Samsung's advanced 1b-nm DRAM process node, each stack integrates twelve DRAM dies interconnected through tens of thousands of Through-Silicon Via (TSV) pillars, enabling the massive internal parallelism that defines HBM architecture. The memory bus width spans 1024 bits per stack, and the device operates at data rates up to 9.8 Gbps per pin, producing an aggregate bandwidth of up to 1.23 TB/s per package — a figure that directly addresses the memory bandwidth bottleneck inherent in large language model inference, training, and scientific simulation workloads.

The 12-high stacking configuration is a significant leap from the 8-high stacks found in prior HBM3 deployments, achieved through thinned die technology and precision bonding that maintains the package height within the JEDEC HBM footprint envelope. Samsung engineered advanced thermal dissipation structures within the stack, including optimized TSV layouts and inter-die underfill materials, to manage the elevated heat density associated with 36GB configurations operating at peak bandwidth. The result is a thermally manageable, dense memory subsystem that pairs directly with GPU dies, ASIC accelerators, and FPGA platforms via silicon interposer or 2.5D packaging.

Launched in Q2 2025, the Samsung HBM3E 12-High targets the most demanding compute workloads where both capacity and bandwidth are simultaneously critical — notably trillion-parameter AI model training, real-time inference on large multimodal models, computational fluid dynamics, molecular dynamics simulation, and seismic processing. The increased per-package capacity reduces the number of stacks required to meet total memory targets on next-generation AI accelerator dies, which in turn simplifies interposer design and can improve overall system power efficiency. This product positions Samsung at the forefront of the HBM roadmap as the industry transitions toward exascale-class AI and HPC infrastructure.

Ideal for

• Large language model (LLM) training requiring simultaneous high memory capacity and ultra-high bandwidth to sustain gradient computation across trillion-parameter architectures
• Real-time generative AI inference serving, where 36GB per stack enables larger model shards to reside on-package and reduces latency from memory-bound operations
• High-performance computing clusters running molecular dynamics, quantum chemistry, and materials science simulations that demand sustained memory bandwidth exceeding 1 TB/s per accelerator
• Computational fluid dynamics and finite element analysis on GPU-accelerated workstations and HPC nodes processing large-mesh scientific datasets
• Seismic data processing and geophysical modeling applications in the energy sector that involve iterative, bandwidth-intensive operations over multi-gigabyte datasets
• Next-generation AI accelerator ASIC development and deployment where 2.5D heterogeneous integration on silicon interposers demands the highest available HBM capacity per package footprint

Technical specifications

Available from Omnixon Global. Submit an RFQ and our team will confirm configuration and availability for your order.