Broadcom PEX 89096 PCIe Gen 5 Smart Switch

The Broadcom PEX 89096 is a 96-lane PCI Express Gen 5 smart switch designed to address the demanding interconnect requirements of next-generation AI servers, composable disaggregated infrastructure, and high-performance computing platforms. Built on Broadcom's advanced silicon process, the PEX 89096 delivers 96 lanes of PCIe Gen 5 bandwidth operating at up to 32 GT/s per lane, providing aggregate switching capacity that scales to meet the GPU-dense topologies found in modern AI training and inference clusters. The device integrates Compute Express Link (CXL) 2.0 protocol support natively, enabling memory pooling, memory expansion, and coherent interconnect between CPUs, GPUs, accelerators, and memory devices without requiring external protocol translation.

The PEX 89096 is architected to support flexible port configurations, allowing system architects to partition lanes into multiple upstream and downstream ports to create fat-tree, mesh, or star topologies that optimize bandwidth utilization between compute nodes and accelerators. Its smart switch capabilities include integrated non-transparent bridging (NTB), autonomous peer-to-peer routing, and hardware-assisted DMA engines that enable GPU-to-GPU direct communication paths, bypassing host CPU involvement and dramatically reducing latency for collective operations in distributed deep learning workloads. The silicon also incorporates advanced QoS and traffic management logic to prioritize latency-sensitive transactions while sustaining high throughput for bulk data transfers.

Targeted at server manufacturers, hyperscale operators, and enterprise AI infrastructure builders, the PEX 89096 serves as the central switching fabric element in 1U, 2U, and 4U AI server designs housing multiple high-end GPUs or AI accelerators. Its support for CXL 2.0 switch topology enables the construction of composable memory and accelerator pools that can be dynamically allocated across compute nodes, aligning with the emerging software-defined infrastructure paradigm. The device is compatible with the PCIe 5.0 and CXL 2.0 specifications ratified by the PCI-SIG and CXL Consortium, ensuring interoperability with Intel Xeon Scalable, AMD EPYC, and ARM-based server processors that expose native CXL-capable root complexes.

Ideal for

• Multi-GPU AI training servers requiring direct GPU-to-GPU peer-to-peer communication fabric to minimize collective communication latency across up to 8 or more accelerators per node
• Composable disaggregated infrastructure deployments where CXL 2.0 memory pooling allows dynamic allocation of DRAM or persistent memory capacity to workloads on demand
• High-density PCIe Gen 5 NVMe storage expansion shelves connected to compute nodes with full bandwidth non-blocking switching for all-flash AI dataset staging
• Hyperscale data center AI inference pods requiring deterministic low-latency PCIe fabric switching between host CPUs and arrays of inference accelerator cards
• SmartNIC and DPU integration platforms where CXL 2.0 coherency enables tight coupling of network offload engines with host memory for zero-copy packet processing
• Modular OCP and Open Rack server chassis designs implementing shared PCIe Gen 5 resource pooling across multiple compute sleds within the same rack unit

Technical specifications

Available from Omnixon Global. Submit an RFQ and our team will confirm configuration and availability for your order.