AMD EPYC 9355 32-Core 3.55GHz Processor (Turin)

The AMD EPYC 9355 is a 32-core, 64-thread server processor built on the Zen 5 microarchitecture (fifth-generation EPYC, codenamed Turin), manufactured on TSMC's 4nm-class process node. With a base clock of 3.55 GHz and a maximum boost clock of up to 3.80 GHz, the 9355 occupies a deliberate position in the Turin lineup that prioritizes sustained high-frequency operation over maximum core count — a profile that directly benefits workloads where per-core clock speed translates into measurable throughput or licensing efficiency. The processor is paired with 96 MB of L3 cache, supports eight channels of DDR5 memory with up to 6000 MT/s speeds, and integrates 128 PCIe 5.0 lanes, enabling high-bandwidth connectivity to NVMe storage, accelerators, and networking adapters.

As part of the EPYC 9005 (Turin) family, the 9355 supports the SP5 socket platform shared across the broader Turin generation, ensuring broad ecosystem compatibility with existing Turin-class server platforms. The processor carries a 200W TDP, placing it in a thermal envelope that balances clock-rate ambition with datacenter power and cooling infrastructure requirements. Support for AMD Infinity Guard security features — including hardware-enforced memory encryption via Secure Memory Encryption (SME) and Secure Encrypted Virtualization (SEV-SNP) — addresses the compliance and isolation requirements of regulated enterprise environments. The 9355 also supports PCIe 5.0 and CXL 2.0, future-proofing platform investments against emerging memory-expansion and composable infrastructure architectures.

Enterprise deployments of the EPYC 9355 are most commonly found in environments where commercial software is licensed on a per-physical-core or per-socket basis — including Oracle Database, SAP HANA scale-up, and Microsoft SQL Server — where reducing core count while maximizing per-core frequency directly lowers total software expenditure without sacrificing transactional throughput. The Zen 5 IPC uplift over the prior generation compounds these frequency advantages, delivering improved branch prediction, wider execution pipelines, and enhanced AVX-512 throughput that benefits analytics, financial modeling, and in-memory database engines.

Ideal for

• License-optimized Oracle Database deployments where per-core software licensing makes high-frequency, moderate-core-count configurations operationally preferable to high-core-count alternatives
• SAP HANA scale-up instances requiring sustained high single-thread and multi-thread performance for real-time in-memory transactional and analytical processing
• Microsoft SQL Server OLTP environments where per-core licensing models reward maximum clock frequency per licensed core for transaction-intensive workloads
• High-frequency financial services applications including real-time risk calculation engines, algorithmic trading platforms, and low-latency order management systems that are sensitive to per-core clock rates
• Virtualization hosts running latency-sensitive consolidated workloads where per-vCPU performance headroom and SEV-SNP-enforced VM isolation are both required
• EDA (Electronic Design Automation) compute clusters and scientific simulation workloads that leverage AVX-512 vector processing and benefit from the Zen 5 generation's improved floating-point throughput

Technical specifications

Available from Omnixon Global. Submit an RFQ and our team will confirm configuration and availability for your order.